Example Schedule

For illustration purposes only

Shows phases only for A0, if A1 or B0 is required we will go through the Spec (if approving deviations), TO and Validation phases again until we can MP sign-off.

* Schedule assumes:

  • High alignment between Supplier existing IP and System Company requirements. Si proposal review is the checkpoint for this.
  • Minimal new IP development. Combining existing blocks.
  • Supplier has excellent integration capability, modern AMS and DV verification flow, and a dedicated verification team. This schedule is impossible for a traditional supplier without modern verification methodologies.
  • Assumes all redesign work can be done in parallel to validation, and no late new bugs found such that as soon as validation is complete we can tape out again.
  • Assumes a simple package like WLCSP.
  • Two schedules are shown for second spin: A1 and B0. It depends on what bugs are found, we may need to do a full layer B0 change, and the cycle time in Fab is longer since there are more layers to be manufactured.

AX,BX,etc…= ‘A’ means base layers revision for the IC, ‘X’ means metal layer revision for the IC.





Concept Phase

Deliverable DRI 2nd DRI Supplier Supports
Concept document sign-off Silicon Manager System lead
High level functional objectives System lead Silicon Manager
High level key parametric objectives System lead Silicon Manager
Target BOM cost System Ops Silicon Manager X
High level system architecture options diagram where this IC fits and pros/cons/risks for each System lead Silicon Manager
Supplier IP search. Identify suppliers that have interesting solutions. Approach them for initial talks. Produce a summary of pros/cons for each option Silicon Manager System lead
Identify stakeholders and get to a sign-off of all parties for a slide set. Silicon Manager System lead
Make a prototype (if possible), and show results. System lead X
Schedule needed to support system builds System PM Silicon Manager X
Preliminary I/O assignment System lead Silicon Manager




Requirements Phase

Deliverable DRI 2nd DRI Supplier Supports
Requirements document sign-off Silicon manager System lead
Detailed functional requirements (refined and more complete than at Concept) System lead Silicon manager
Detailed parametric requirements System lead Silicon manager
Target BOM cost Silicon manager System lead X
Detailed system architecture diagram where this IC fits System lead Silicon manager
Send official RFQ/RFI to suppliers Silicon manager System Ops
Si Proposal review and Supplier Selection - > First in depth review with the Supplier Silicon manager X
Detailed schedule needed to support system builds. System PM Silicon manager
Identify stakeholders and get to a sign-off of all parties for a slide set. Silicon manager
Identify deltas between concept functional or parametric objectives and requirements. Silicon manager System lead
Board space requirements (mm˛), power budget and modes of operation requirements. System lead Silicon manager
Detailed I/O assignment System lead Silicon manager X
Requirements review/discussion with suppliers. Silicon manager System lead
Define required memory, and registers for system use. System lead Silicon manager




Specification Phase

Deliverable DRI 2nd DRI Supplier Supports
Specification document sign-off (this is the datasheet that the supplier proposes to design to): Silicon manager Supplier PM X
Draft Specification review ( Supplier to provide this) Supplier PM Silicon manager X
Identify deltas between signed off requirements and proposed specification Supplier PM Silicon manager X
Drive specification negotiation between System team and Supplier Silicon manager Supplier PM X
BOM cost Supplier PM Silicon manager X
I/O assignment System lead Supplier PM X
Package drawing Supplier Packaging Silicon manager X
Board space requirements (mm^2), power budget and modes of operation defined. System lead Silicon manager X
Define state machines, interfaces, memory, OTP and register definitions. Supplier PM System lead X
Final specification review Silicon manager System lead X
Schedule Supplier PM Silicon manager X
Identify stakeholders and get to a sign-off of all parties for a slide set. Silicon manager




Tape Out Phase

Deliverable DRI 2nd DRI Supplier Supports
Tape out sign-off (Slides containing all of the below) Silicon manager System lead
Review of analog simulation plan and results. Identify types of simulation to be run; mismatch, corners, temperature, etc... Silicon manager System lead X
Review of System use case simulation plan and results Silicon manager System lead X
Review AMS verification plan and results Silicon manager System lead X
Review DV simulation plan and results (Clocks, clock shields, Interfaces, Resets, Power supply present for clock domain, RTL checks, etc...) Silicon manager System lead X
Review Supplier FPGA verification Silicon manager System lead X
Review Tape out (DRC, antenna, ERC, etc...) and CAD tools used Silicon manager Supplier PM X
Schedule Supplier PM Silicon manager X
Design review (optimally two design reviews, one midpoint and one final). Silicon manager Supplier PM X
Package simulations (warpage, thermal) Supplier Packaging System rel & Silicon manager X
Waivers for specification deviations. Amended specification if waivers are approved by System team. System lead Silicon manager X
Identify stakeholders and get to a sign-off of all parties for a slide set. Silicon manager System lead
BOM cost Supplier PM Silicon manager X
Corner wafer plan Supplier PM Silicon manager X
Package drawing (final) Supplier Packaging Silicon manager X
Volume support plan: ATE site(s) and wafer fab(s) planned. Supplier PM Silicon manager X




Validation Phase

Deliverable DRI 2nd DRI Supplier Supports
Validation report review and sign-off ( chip supplier provides their report) - usually combined with Tape out sign off or Mass production sign off Silicon manager X
Review supplier ATE validation plan. Silicon manager TE supplier
Generate System validation plan. Silicon manager System lead
ATE validation results for corner parts and/or large quantity results. Check CPK and confirm spec limits. TE supplier Silicon manager X
Bench validation results Supplier PM X
System validation results (nominal part builds and corner part builds System lead Silicon manager
Review all bugs and determine whether to waive or fix. System lead Silicon manager X
Review spec limits, waive any violations for yield improvement or decide to fix silicon. Silicon manager System lead X
Review all proposed ECOs to assess feasibility and risks Silicon manager System lead X




Mass Production Phase

Deliverable DRI 2nd DRI Supplier Supports
MP sign-off (this is a combination of supplier MP validation and System validation) Silicon manager X
Ramp up plan including risk ramp planning and risk mitigation System Ops Silicon manager X
Approve wafer kick off to support mass production System lead System Ops X
Review all validation Silicon manager System lead X
Review JEDEC qualification tests Silicon manager System rel or System component engineering X
Review system stress testing results System rel
Work on SOW with chip supplier System legal Silicon manager X




Out of bounds reviews

Deliverable DRI 2nd DRI Supplier Supports
OOB sign-off (this is a review that is held whenever the project needs to decommit from schedule or some other major cost or performance change is requested by the team). Silicon manager X
Provide updated cost, schedule and spec Supplier PM Silicon manager X




Si Proposal Review

During the proposal review, the System Company would like to review the following with Supplier:

  • Description of all deltas required for each silicon subsystem block to be able to meet our requirements. Explain who will implement the change and have that person available to present the information themselves, show some schematics and describe the change in detail. Explain IP re-use and IP process porting (if any), and process and device qualification status.
  • Team members brief bio and relevant projects that support experience in the area to which they have been assigned in the project.
  • Schedule and price estimate.
  • Line by line response to our Concept requirements stating whether the requirement can be supported, and stating technical and schedule risk.
  • Provide proposal on how to unblock FW dev while Custom IC is unavailable.
  • Provide detailed description of your verification methodology for DV and AMS.